In general, CMOS semiconductor devices include integrated circuits having complementary pairs of P-channel field-effect transistors and N-channel field-effect transistors formed on a common semiconductor substrate. As is generally known in the art, CMOS technologies are typically used to fabricate IC (integrated circuit) chips for high density and high-performance applications due to, e.g., the high operation efficiency, high switching speed, and good scaling properties that are characteristic of CMOS devices. Technological innovations in semiconductor fabrication technologies are driving market demands for CMOS solutions for higher speed, higher integration density, and lower power applications. The downscaling of CMOS technologies to submicron design rules and beyond, however, poses technological challenges with respect to maintaining performance and reliability. For example, as device sizes are downscaled, CMOS transistors must be formed with, e.g., thinner gate electrodes, smaller channel lengths, and shallower drain/source extension diffusion regions. This downscaling generally results in transistors having higher channel resistance and higher junction/contact parasitic resistances, leading to degraded performance.
To mitigate the impact on device performance with downscaling, various state of the art CMOS fabrication techniques can be implemented to effectively reduce parasitic gate and junction resistances and increase channel conductivity. For example, DSL (dual stress liner) techniques can be incorporated in CMOS process flows as a means to enhance performance of highly-scaled CMOS devices. In general, DSL technologies are premised on findings that the application of compressive stress to the conduction channel of a P-type transistor can improve the carrier (holes) mobility within the channel, while the application of tensile stress to the conduction channel of an N-type transistor can improve the carrier (electrons) mobility within the channel. In this regard, various DSL techniques have been developed to form a compressive stress insulating liner over the gate structure of P-type transistors while forming tensile stress insulating liners over the gate structures of N-type transistor devices, so as to increase charge carrier mobility in the channels of the complementary transistors.
FIG. 1 is a cross-sectional schematic view of a dual stress liner CMOS device having a conventional framework. FIG. 1 illustrates a CMOS semiconductor device (100) having NMOS and PMOS transistor structures (110) and (120) formed in respective active regions (102) and (103) on an active surface of a semiconductor substrate (101). The active regions (102) and (103) are defined and separated by an isolation structure (104) (e.g., STI (shallow trench isolation) structure). In the illustrative embodiment, the active region (102) is defined by a portion of a P-type substrate layer (101a) and the active region (103) comprises an N-type device well (101b) formed in the P-type substrate layer (101a). The NMOS transistor (110) comprises a gate structure (111) formed on the substrate surface in the active region (102), as well as n-doped drain/source diffusion regions (16) formed in the p-type substrate layer (101a). Similarly, the PMOS transistor (120) comprises a gate structure (121) formed on the substrate surface in the active region (103), as well as p-doped drain/source diffusion regions (16) formed in the N-well (101b). The source/drain regions (16) of the transistors (110) and (120) include metal silicide contact regions (17).
The gate structures (111) and (121) have similar structures, each comprising a polysilicon (poly-Si) gate electrode (11/12/13) formed of stacked layers including a dielectric layer (11), a polysilicon layer (12) and a metal silicide layer (13). Moreover, the gate structures (111) and (121) each have thin L-shaped sidewall insulating spacer layers (14) formed on the sidewalls of the gate electrodes (11/12/13) and a portion of the surface of the active silicon regions adjacent the sidewalls. A polyconductor structure (131) is formed over the isolation region (104), which comprises a polysilicon layer (12′) and metal silicide layer (13′) similar to the gate structures (111) and (121). As is known in the art, the polyconductor structure (131) may be part of an electrical interconnection that is formed simultaneously and integrally with the gate structures (111) and (121), which serves to connect the gate electrodes of the complementary transistor pairs (110) and (120), for example.
Further, different stress liner layers (140, 160) are formed over the active surface of the semiconductor substrate (101) to form a DSL structure that imparts appropriate stresses to enhance the channel conductivity of the CMOS transistors (110) and (120). For such CMOS devices employing dual liners, a conventional approach has been to form the two different stress liner layers (140) and (160) using separate lithographic patterning steps. For example, the stress liner layer (140) and optional oxide film (150) can be formed by depositing a tensile silicon nitride film and oxide film over both PFET and NFET device regions, followed by a photolithographic patterning process to pattern the stress liner layer (140) and oxide layer (150) to remove the portions of the stress liner layer (140) and oxide layer (150) over the NFET device region (103). Thereafter, the stress liner layer (160) can be formed by depositing a compressive silicon nitride film over the NFET and PFET device regions (102) and (103), followed by a second photolithographic patterning process to pattern the stress liner layer (160) and remove the portions of the stress liner layer (160) and oxide layer (150) over the PFET device region (103). In this process, the stress liner layers (140) and (160) are formed using separate lithographic patterning steps.
Due to inherent limitations associated with aligning subsequent photolithographic levels to previous levels, the various DSL structure layers (140), (150) and (160) may be formed in a manner, such as depicted in FIG. 1, where the compressive stress liner (160) overlaps the tensile nitride liner (140) and oxide layer (150). This overlap ensures that no gap is formed between the two stress liner layers (140) and (160) due to misalignment of the two photolithographic processes. This conventional process results in a DSL structure having a non-uniform thickness. For example, in the illustrative embodiment of FIG. 1, the overlapping portion of the DSL structure has a thickness equal to the combined thickness t1 of the first stress liner layer (140) and the thickness t2 of the second stress liner layer (160), plus some smaller added thickness of the oxide layer (150). In this regard, the dual stress liner structure has non-uniform thickness in different regions. The non-uniform thickness of the DSL structure may be problematic with regard to subsequent processing steps.
By way of example, the non-uniformity in thickness of the DSL structure may cause problems during subsequent BEOL processing when etching contact via holes through the different regions (overlapped and non-overlapped regions) of the DSL structure to form contacts to underlying polysilicon contact regions (13), (13′) and (17). In some conventional techniques, a reactive ion etch (RIE) process is used to concurrently etch openings in the DSL layers to expose the metal silicide regions (13), (13′) and (17) in both the overlapped region (105) and non-overlapped regions of the DSL layers. To accommodate for the non-uniform thickness of the DSL layers, an over-etch RIE process is performed to ensure that a contact opening is sufficiently formed in the overlapped region (105) to expose the underlying metal contact (13′). Such over-etching, however, can cause damage to and/or erosion of the metal silicide regions (13) and (17) in the non-overlapping regions of the DSL structure which are first exposed and remain exposed during over etching of via contacts in the overlapped region (105) to sufficiently expose the silicide contacts (13′). In some instances, severe over etching can result in defects such as punch through the silicide contact layers (13) and (17) or unwanted residual material, all of which causing higher resistance contact interfaces between device contacts and the metal plugs subsequently formed in the contact holes during later stages of BEOL fabrication.